References
A good high level introduction to the technical philosophy behind Centar's
architecture can be found in the article "Rethinking
the FFT" and "Non-Power-of-Two
Designs Do Not Have to Be Difficult" (and the Introduction and
Background in the Electronics paper in the list below):
Several more technical papers are available describing some of the FFT features:
- “Distributed-Memory-Based FFT Architecture and FPGA Implementations” J. Greg Nash, Electronics, 7 (7) 116, June 2018
- “Efficient
Circuit Architecture and FPGA Implementation for LTE Single Carrier FDMA DFT,”
latest circuit summary, to be presented at 2016 Int. System-on-Chip Conf.,
Seattle, WA, Sept. 2016 (associated
presentation).
- “High-Throughput Programmable Systolic Array FFT Architecture and FPGA Implementations,”
latest circuit summary, to be presented at 2014 International Conference on
Computing and Networking, Honolulu, HI, Feb. 2014 (associated
presentation).
- “A New Class of High Performance FFTs” describes Centar’s first “demonstration” 16-bit 256-point and 1024-point FPGA circuit designs (associated
presentation).
- “A High Performance Scalable FFT” and “An FFT for Wireless Protocols” are papers that focus on the FPGA circuit design of a 256-point FFT and its application to 4G wireless systems. (Corresponding presentations are
here and
here.)
- “ A High Performance Block Floating Point Systolic FFT Not Limited to Powers of Two
” and “Computationally Efficient Systolic Architecture for Computing the Discreet Fourier Transform” focuses on the algorithm derivation and architecture. In addition a PowerPoint
presentation are available summarizing the architecture in more visual form.
- “Constraint Directed CAD Tool For Automatic Latency-Optimal Implementation of 1-D and 2-D Fourier Transforms” deals primarily with issues related to use of a CAD tool to automatically derive the base-4 systolic architecture
Datasheets