||"Distributed-Memory-Based FFT Architecture and FPGA Implementations"
published in Electronics (see Quick Links at home page).
||New IEEE 754 designs on Intel Arria 10 FPGAs with embedded support for
floating-point operations show drastic reductions in LUTs and registers.
||"LTE Single Carrier DFT: Faster Circuits with Reduced FPGA LUT/Register
Usage" published (see "Quick
Links" at home page) comparing Xilinx and Altera equivalent designs.
||Paper accepted for presentation at 2016 IEEE Int. System-on-Chip Conf.,
Seattle, WA: “Efficient Circuit Architecture and FPGA Implementation for LTE
Single Carrier FDMA DFT”.
||Migrated LTE SC-FDMA design to Xilinx FPGA platform
||Sucessfully delivered non-power-of-two design to customer
||New (IEEE754) floating point 256/1024-point designs completed, including
simulation verification (SQNR approximately 149/151db).
||"Non-Power-of-Two-Designs Do Not Have to be Difficult" published (see "Quick
Links" at home page) summarizing how Centar's architecture makes this possible.
||"Rethinking the FFT" published (see "Quick Links" at home page) explaining
why Centar's unique and novel FFT features make it a better choice for most high
||Paper presented at 2014 Computer Networking and Communication Conference, February 2014: “High Throughput Programmable Systolic Array FFT Architecture and FPGA Implementatons”.
||New LTE variable FFT design with 128/256/512/1024/2048 points completed, supporting both short and long cyclic prefixes (see new datasheet). Fmax at 501 MHz demonstrated based on Quartus Timequest timing analysis.
||Cyclic prefix option added to all FFT circuits. Any prefix value up to the transform size N can be programmed.
||Successful demonstration of LTE SC-FDMA circuit (35 DFT sizes) running at 450MHz sample rate on Altera® Stratix® III Development Kit board with Stratix III EP3SE50F484C2 FPGA, >100% faster than equivalent Xilinx and Altera IP
||Successful demonstration of variable FFT (128/256/512/1024/2048 points) running at record 500MHz sample rate on Altera® Stratix® III Development Kit board with Stratix III EP3SE50F484C2 FPGA
||Centar wins Technology Enhancement for Commercial Partnerships contract from the National Science Foundation
||Demonstration of translation program to automatically produce Verilog code for circuits of arbitrary fixed-point word length
||Invited talk on FFT technology at National Science Foundation Technology exchange program, Baltimore, MD.
||Centar wins Phase II National Science Foundation Small Business Innovation Research contract.
|| ” A High Performance Scalable FFT”, presented at IEEE Int. Conf. Wireless Communications & Networking Conference, Hong Kong.
|| ”A New Class of High Performance FFTs,” presented at IEEE Int. Conf. Accoustics, Speech and Signal Processing, Honolulu, HI.
||Centar wins Phase I National Science Foundation Small Business Innovation Research contract.
|| ” A High Performance Block Floating Point Systolic FFT Not Limited to Powers of Two,” presented at GSPx, Santa Clara, CA.
|| ”Computationally Efficient Systolic Array for Computing the Discreet Fourier Transform” accepted for publication in IEEE Trans. Signal Processing.