FFT Circuitry for a 4G Age
Centar LLC is a provider of fast Fourier transform (FFT) intellectual property (IP) for use in FPGA and ASIC-based embedded applications. It has developed a novel parallel matrix-based formulation of the discreet Fourier transform (DFT), which decomposes it into structured sets of b-point discreet Fourier transforms. All FFT circuits are constructed from synchronous, fine-grained, locally connected, regular arrays of small processing elements (PEs), consisting of a few registers, some multiplexors and an arithmetic element. Salient features of this technology are:
  • Speed: The only FPGA FFT circuits with clock rates >500MHz using 65nm technology (e.g., Altera Stratix III).
  • Throughput: Data rates as high as ~10G complex samples per second
  • Dynamic Range: Combined block floating point and floating point architecture means smaller word lengths can be used
  • Programmability: Easy customization of FFT properties, functionality and I/O interface.
  • Non-powers-of-two transform sizes: A single ROM memory can store control parameters to support any number or size FFTs
  • Scalability: Faster transforms can be implemented without architectural changes by increasing the array size along one dimension or duplicating the array structure
  • Power: Interconnects are entirely local, reducing parasitic routing capacitances to keep power dissipation low and speed high
  • Cyclic Prefix: Circuit architecture is designed to support any prefix value (most FFT circuits require additional circuits to perform this function)


  • Power-of-two FFT: Fixed and variable (run-time selectable) size, 16 to 16,384 points.
Altera Centar v1 Centar v2 Altera Centar
Transform Size 256pts 1024pts
ALMs/M9Ks 4261/38 3982/31 5063/15 4394/38 4331/31
Transform Time (usec) 0.66 0.45 0.45 2.68 1.95
SQNR 76.6 86.7 86.7 81.3 82.9
Example: comparative metrics for "streaming" circuits targeted to Stratix III FPGAs (C2 speed grade).
  • Non-power-of-two FFT: The reachable transform sizes for this class of designs are those that can be factored into a composite form based on small integers up to sizes of ~10. For example, the SC-FDMA LTE requirements would use the integers {2,3,5} to compute all 35 transform sizes, e.g., N=2n3m5q, where n,m, and q are integers. These can be fixed-size or variable and selectable at run-time.
Average Latency Average Throughput Resource Block Computation Time 1200 point Computation Time
Altera 2.1 0.33 3.0 2.8
Xilinx 1.2 0.46 2.1 2.0
Centar 1.0 1.0 1.0 1.0
Example: LTE SC-FDMA relative performance for 65nm FPGA technology (average over 35 different DFT sizes).


Because there are always a large number of (parallel) circuit architectures that can be obtained from an algorithm specification, Centar has developed an automated CAD tool, Symbolic Parallel Algorithm Development Environment (SPADE), to make the best choices. SPADE is the only such tool in existence that can find latency optimal circuits.