Centar LLC is a provider of fast Fourier transform (FFT) intellectual property (IP) for use in FPGA and ASIC-based embedded applications. It has developed a novel parallel matrix-based formulation of the discreet Fourier transform (DFT), which decomposes it into structured sets of b
-point discreet Fourier transforms. All FFT circuits are constructed from synchronous, fine-grained, locally connected, regular arrays of small processing elements (PEs), consisting of a few registers, some multiplexors and an arithmetic element. Salient features of this technology are:
- Speed: The only FPGA FFT circuits with clock rates >500MHz using 65nm technology (e.g.,
Intel Stratix III).
- Throughput: Data rates as high as ~10G complex samples per second
- Dynamic Range: Combined block floating point and floating point architecture means smaller word lengths can be used
for post processing operations such as equalization.
- Programmability: Easy customization of FFT properties, functionality and I/O interface.
- Non-powers-of-two transform sizes: A single ROM memory can store control parameters to support any number or size FFTs
- Scalability: Faster transforms can be implemented without architectural changes by increasing the array size along one dimension or duplicating the array structure
- Power: Interconnects are entirely local, reducing parasitic routing capacitances to keep power dissipation low and speed high
- Cyclic Prefix: Circuit
architecture is designed to support any prefix value (most FFT circuits
require additional circuits to perform this function
- Floating-Point (NEW): IEEE754 single precision
floating-point, fixed-size Stratix streaming circuits use far less of the
FPGA fabric (1024-point FFT uses half the number of ALMs compared to the
Also, Centar's new Arria 10 circuits run at a 571 MHz sampling rate and,
with hardwired floating-point DSPs, only use 2234 ALMs for an entire
- Power-of-two FFT: Fixed and variable (run-time selectable) size, 16 to 16,384 points.
|FFT Time (usec)
Example: comparative metrics for "streaming" circuits targeted to
Stratix III, IV and Arria 10 FPGAs.
Example: LTE SC-FDMA relative performance, average over 35 different DFT sizes.
(For details click here.)
Because there are always a large number of (parallel) circuit architectures that can be obtained from an algorithm specification, Centar has developed an automated CAD tool, Symbolic Parallel Algorithm Development Environment (SPADE), to make the best choices. SPADE is the only such tool in existence that can find latency optimal circuits.