FFT Circuitry for a *4G* Age

Centar LLC is a provider of fast Fourier transform (FFT) intellectual property (IP) for use in FPGA and ASIC-based embedded applications. It has developed a novel parallel matrix-based formulation of the discreet Fourier transform (DFT), which decomposes it into structured sets of *b*-point discreet Fourier transforms. All FFT circuits are constructed from synchronous, fine-grained, locally connected, regular arrays of small processing elements (PEs), consisting of a few registers, some multiplexors and an arithmetic element. Salient features of this technology are:
## Products

Example: comparative metrics for "streaming" circuits targeted to Stratix III and IV FPGAs (C2 speed grade).

Example: LTE SC-FDMA relative performance for 65nm FPGA technology (average over 35 different DFT sizes).
## Tools

Because there are always a large number of (parallel) circuit architectures that can be obtained from an algorithm specification, Centar has developed an automated CAD tool, Symbolic Parallel Algorithm Development Environment (SPADE), to make the best choices. SPADE is the only such tool in existence that can find latency optimal circuits.

: The only FPGA FFT circuits with clock rates >500MHz using 65nm technology (e.g., Altera Stratix III).**Speed**: Data rates as high as ~10G complex samples per second**Throughput**: Combined block floating point and floating point architecture means smaller word lengths can be used for post processing operations such as equalization.**Dynamic Range**: Easy customization of FFT properties, functionality and I/O interface.**Programmability**: A single ROM memory can store control parameters to support any number or size FFTs**Non-powers-of-two transform sizes**: Faster transforms can be implemented without architectural changes by increasing the array size along one dimension or duplicating the array structure**Scalability**: Interconnects are entirely local, reducing parasitic routing capacitances to keep power dissipation low and speed high**Power****Cyclic Prefix****:**Circuit architecture is designed to support any prefix value (most FFT circuits require additional circuits to perform this function)IEEE754 single precision floating point fixed-size streaming circuits use much less memory and far fewer LUTs (1024-point uses half the number of ALMs compared to the Altera's equivalent)*Floating Point*:

: Fixed and variable (run-time selectable) size, 16 to 16,384 points.**Power-of-two FFT**

Altera | Centar v1 | Centar v2 | Altera | Centar | Altera | Centar | Altera | Centar | |

Transform Size | 256pts (fixed point) | 1024pts (fixed point) | 256pts (IEEE754) | 1024pts (IEEE754) | |||||

ALMs/M9Ks | 4414/38 | 4024/31 | 5063/15 | 4770/38 | 4357/31 | 10545/57 | 7424/30 | 12883/90 | 6662/62 |

Transform Time (usec) | 0.68 | 0.48 | 0.45 | 2.72 | 1.92 | 0.83 | 0.7 | 3.4 | 3.3 |

SQNR or mean error | 76.6 | 86.7 | 86.7 | 81.3 | 82.9 | 8.6e-8 | 3.1e-8 | 8.8e-8 | 4.2e-8 |

mJ/FFT | 1.29 | 1.12 | 6.36 | 4.31 | |||||

FPGA | Straitx III | Straitx III | Straitx III | Straitx III | Straitx III | Stratix IV | Stratix IV | Stratix IV | Stratix IV |

Example: comparative metrics for "streaming" circuits targeted to Stratix III and IV FPGAs (C2 speed grade).

The reachable transform sizes for this class of designs are those that can be factored into a composite form based on small integers up to sizes of ~10. For example, the SC-FDMA LTE requirements would use the integers {2,3,5} to compute all 35 transform sizes, e.g.,**Non-power-of-two FFT:***N=2*, where^{n}3^{m}5^{q}*n*,*m*, and q are integers. These can be fixed-size or variable and selectable at run-time.

Average Latency | Average Throughput | Resource Block Computation Time | 1200 point Computation Time | |

Altera | 2.1 | 0.33 | 3.0 | 2.8 |

Xilinx | 1.2 | 0.46 | 2.1 | 2.0 |

Centar | 1.0 | 1.0 | 1.0 | 1.0 |

Example: LTE SC-FDMA relative performance for 65nm FPGA technology (average over 35 different DFT sizes).